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? freescale semiconductor, inc., 2003, 2005, 2009. all rights reserved. freescale semiconductor this document contains information on a new product. specifications and information herein are subject to change without notice. this document contains de tailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications for the mpc8250 powerquicc ii? communications processor. the following topics are addressed: the mpc8250 is available in two packages?the standard tbga package (480 pins) and an alternate pbga package (516 pins)?as described in section 4, ?pinout ,? and section 5, ?package description .? for more information on pbga packages, contact your freescale sales office. note that throughout this document references to the mpc8250 are inclusive of its pbga version unless otherwise specified. document number: mpc8250ec rev. 2, 07/2009 contents 1. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical and thermal characteristics . . . . . . . . . . . . 6 3. clock configuration modes . . . . . . . . . . . . . . . . . . . 20 4. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. package description . . . . . . . . . . . . . . . . . . . . . . . . . 55 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 59 7. document revision history . . . . . . . . . . . . . . . . . . . 59 mpc8250 hardware specifications
mpc8250 hardware specifications, rev. 2 2 freescale semiconductor features figure 1 shows the block diagram for the mpc8250. figure 1. mpc8250 block diagram 1 features the major features of the mpc8250 are as follows: ? footprint-compatible with the mpc8260 ? dual-issue integer core ? a core version of the ec603e microprocessor ? system core microprocessor s upporting frequencies of 150?200 mhz ? separate 16-kbyte data and instruction caches: ? four-way set associative ? physically addressed ? lru replacement algorithm ? powerpc architecture-compliant memory management unit (mmu) ? common on-chip processor (cop) test interface ? high-performance (4.4?5.1 spec95 benchmark at 200 mhz; 280 dhrystones mips at 200 mhz) 16 kbytes g2 core i-cache i-mmu 16 kbytes d-cache d-mmu communication processor module (cpm) timers parallel i/o baud rate generators 32 kbytes 32-bit risc microcontroller and program rom serial dmas 4 virtual idmas 60x-to-pci bridge bridge memory controller clock counter system functions system interface unit (siu) local bus 32 bits, up to 66 mhz pci bus 32 bits, up to 66 mhz or mcc2 fcc1 fcc2 fcc3 scc1 scc2 scc3 scc4 smc1 smc2 spi i 2 c serial interface 3 mii ports 60x bus dual-port ram interrupt controller time slot assigner 4 tdm ports non-multiplexed i/o 60x-to-local bus interface unit
mpc8250 hardware specifications, rev. 2 freescale semiconductor 3 features ? supports bus snooping for data cache coherency ? floating-point unit (fpu) ? separate power supply for internal logic (1.8 v) and for i/o (3.3v) ? separate plls for g2 core and for the cpm ? g2 core and cpm can run at different frequencies for power/performance optimization ? internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios ? internal cpm/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios ? 64-bit data and 32-bit address 60x bus ? bus supports multiple master designs ? supports single- and four-beat burst transfers ? 64-, 32-, 16-, and 8-bit port sizes c ontrolled by on-chip memory controller ? supports data parity or ecc and address parity ? 32-bit data and 18-bit address local bus ? single-master bus, supports external slaves ? eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller ? 60x-to-pci bridge ? programmable host bridge and agent ? 32-bit data bus, 66 mhz, 3.3 v ? synchronous and asynchronous 60x and pci clock modes ? all internal address space available to external pci host ? dma for memory block transfers ? pci-to-60x address remapping ? system interface unit (siu) ? clock synthesizer ? reset controller ? real-time clock (rtc) register ? periodic interrupt timer ? hardware bus monitor and software watchdog timer ? ieee 1149.1? jtag test access port ? twelve-bank memory controller ? glueless interface to sram, page mode sdram, dram, eprom, flash and other user- definable peripherals ? byte write enables and selectable parity generation ? 32-bit address decodes with programmable bank size ? three user programmable machines, general-purpose chip-select machine, and page-mode pipeline sdram machine ? byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
mpc8250 hardware specifications, rev. 2 4 freescale semiconductor features ? dedicated interface logic for sdram ? cpu core can be disabled and the device can be used in slave mode to an external core ? communications processor module (cpm) ? embedded 32-bit communications processor (cp) uses a risc architecture for flexible support for communications protocols ? interfaces to g2 core through on-chip 32-kbyte dual-port ram and dma controller ? serial dma channels for receive and transmit on all serial channels ? parallel i/o registers with open-drain and interrupt capability ? virtual dma functionality executing memory-to-memory and memory-to-i/o transfers ? three fast communications controllers supporting the following protocols: ? 10/100-mbit ethernet/ieee 802.3? cdma/cs interface through media independent interface (mii) ? transparent ? hdlc?up to t3 rates (clear channel) ? one multichannel controller (mcc2) ? handles 128 serial, full-duplex, 64-kbps data channels. the mcc can be split into four subgroups of 32 channels each. ? almost any combination of subgroups can be multiplexed to single or multiple tdm interfaces up to four tdm interfaces per mcc ? four serial communications controllers (sccs) identical to those on the mpc860, supporting the digital portions of the following protocols: ? ethernet/ieee 802.3 cdma/cs ? hdlc/sdlc and hdlc bus ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? binary synchronous (bisync) communications ? transparent ? two serial management controllers (smcs), identical to those of the mpc860 ? provide management for bri devices as general circuit interface (gci) controllers in time- division-multiplexed (tdm) channels ? transparent ? uart (low-speed operation) ? one serial peripheral interface identical to the mpc860 spi ? one inter-integrated circuit (i 2 c) controller (identical to the mpc860 i 2 c controller) ? microwire compatible ? multiple-master, single-master, and slave modes ? up to four tdm interfaces ? supports one group of four tdm channels
mpc8250 hardware specifications, rev. 2 freescale semiconductor 5 features ? 2,048 bytes of si ram ? bit or byte resolution ? independent transmit and receive routing, frame synchronization ? supports t1, cept, t1/e1, t3/e3, pulse code modulation highway, isdn basic rate, isdn primary rate, freescale interchip digital link (idl), general circuit interface (gci), and user-defined tdm serial interfaces ? eight independent baud rate ge nerators and 20 input clock pins for supplying clocks to fccs, sccs, smcs, and serial channels ? four independent 16-bit timers that can be interconnected as two 32-bit timers ? pci bridge ? pci specification revision 2.2 compliant and supports frequencies up to 66 mhz ? on-chip arbitration ? support for pci to 60x memory and 60x memory to pci streaming ? pci host bridge or periphera l capabilities ? includes 4 dma channels for the following transfers: ? pci-to-60x to 60x-to-pci ? 60x-to-pci to pci-to-60x ? pci-to-60x to pci-to-60x ? 60x-to-pci to 60x-to-pci ? includes all of the configuration registers (which are automatically loaded from the eprom and used to configure the mpc8265a) required by the pci standard as well as message and doorbell registers ? supports the i 2 o standard ? hot-swap friendly (supports the hot swap sp ecification as defined by picmg 2.1 r1.0 august 3, 1998) ? support for 66 mhz, 3.3 v specification ? 60x-pci bus core logic which uses a buffer pool to allocate buffers for each port ? makes use of the local bus signals, so there is no need for additional pins
mpc8250 hardware specifications, rev. 2 6 freescale semiconductor electrical and thermal characteristics 2 electrical and thermal characteristics this section provides ac and dc electrical specif ications and thermal characteristics for the mpc8250. 2.1 dc electrical characteristics this section describes the dc electrical characteristics for the mpc8250. table 1 shows the maximum electrical ratings. table 2 lists recommended operati onal voltage conditions. table 1. absolute maximum ratings 1 1 absolute maximum ratings are stress ratings only; functional operation (see tab le 2 ) at the maximums is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage. rating symbol value unit core supply voltage 2 2 caution: vdd/vccsyn must not exceed vddh by more than 0.4 v at any time, including during power-on reset. vdd -0.3 ? 2.5 v pll supply voltage 2 vccsyn -0.3 ? 2.5 v i/o supply voltage 3 3 caution: vddh can exceed vdd/vccsyn by 3.3 v during power on reset by no more than 100 msec. vddh should not exceed vdd/vccsyn by more than 2.5 v during normal operation. vddh -0.3 ? 4.0 v input voltage 4 4 caution: vin must not exceed vddh by more than 2.5 v at any time, including during power-on reset. vin gnd(-0.3) ? 3.6 v junction temperature t j 120 c storage temperature range t stg (-55) ? (+150) c table 2. recommended operating conditions 1 1 caution: these are the recommended and tested operating conditions. proper device operating outside of these conditions is not guaranteed. rating symbol value unit core supply voltage vdd 1.7 ? 1.9 2 2 cpu frequency less than or equal to 200 mhz. 1.7?2.1 3 3 cpu frequency greater than 200 mhz but less than 233 mhz. 1.9 ?2.2 4 4 cpu frequency greater than or equal to 233 mhz. v pll supply voltage vccsyn 1.7 ? 1.9 2 1.7?2.1 3 1.9?2.2 4 v i/o supply voltage vddh 3.135 ? 3.465 v input voltage vin gnd (-0.3) ? 3.465 v junction temperature (maximum) t j 105 5 5 note that for extended temperature parts the range is (-40) t a ? 105 t j . c ambient temperature t a 0?70 5 c
mpc8250 hardware specifications, rev. 2 freescale semiconductor 7 electrical and thermal characteristics note: core, pll, and i/o supply voltages vddh, vccsyn, and vdd must track each other and both must vary in the same direction?in the positive direction (+5% and +0.1 vdc) or in the negative direction (-5% and -0.1 vdc). this device contains circuitry protecting against dama ge due to high static voltage or electrical fields; however, it is advised that normal precautions be take n to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circ uit. reliability of operation is enhanced if unused inputs are tied to an appropriate l ogic voltage level (either gnd or v cc ). figure 2 shows the undershoot and overshoot voltage of th e 60x and local bus memory interface of the mpc8280. note that in pci mode the i/o interface is different. figure 2. overshoot/undershoot voltage table 3 shows dc electrical characteristics. table 3. dc electrical characteristics 1 characteristic symbol min max unit input high voltage, all inputs except clkin v ih 2.0 3.465 v input low voltage v il gnd 0.8 v clkin input high voltage v ihc 2.4 3.465 v clkin input low voltage v ilc gnd 0.4 v input leakage current, v in = vddh 2 i in ?10a hi-z (off state) leakage current, v in = vddh 2 i oz ?10a signal low input current, v il = 0.8 v i l ?1 a signal high input current, v ih = 2.0 v i h ?1 a output high voltage, i oh = ?2 ma v oh 2.4 ? v gnd gnd ? 0.3 v gnd ? 1.0 v not to exceed 10% gv dd of t sdram_clk gv dd + 5% 4 v v ih v il
mpc8250 hardware specifications, rev. 2 8 freescale semiconductor electrical and thermal characteristics i ol = 7.0ma br bg abb/irq2 ts a[0-31] tt[0-4] tbst tsize[0?3] aack artry dbg dbb /irq3 d[0-63] dp(0)/rsrv /ext_br2 dp(1)/irq1 /ext_bg2 dp(2)/tlbisync /irq2 /ext_dbg2 dp(3)/irq3 /ext_br3 /ckstp_out dp(4)/irq4 /ext_bg3 /core_srest dp(5)/tben/irq5 /ext_dbg3 dp(6)/cse(0)/irq6 dp(7)/cse(1)/irq7 psdval ta tea gbl /irq1 ci/ baddr29/irq2 wt /baddr30/irq3 l2_hit /irq4 cpu_bg/ baddr31/irq5 cpu_dbg cpu_br irq0 /nmi_out irq7 /int_out /ape poreset hreset sreset rstconf qreq v ol ?0.4 v table 3. dc electrical characteristics 1 (continued) characteristic symbol min max unit
mpc8250 hardware specifications, rev. 2 freescale semiconductor 9 electrical and thermal characteristics i ol = 5.3ma cs [0-9] cs (10)/bctl1 cs (11)/ap(0) baddr[27?28] ale bctl0 pwe (0:7)/psddqm( 0:7)/pbs (0:7) psda10/pgpl0 psdwe/ pgpl1 poe/psdras/pgpl2 psdcas/pgpl3 pgta/pupmwait/pgpl4/ppbs psdamux/pgpl5 lwe[0?3]lsddqm[0:3]/lbs[0?3]/pci_cfg[0?3 lsda10/lgpl0/pci_modckh0 lsdwe/lgpl1/pci_modckh1 loe/lsdras/lgpl2/pci_modckh2 lsdcas/lgpl3/pci_modckh3 lgta/lupmwait/lgpl4/lpbs lsdamux/lgpl5/pci_modck lwr modck1/ap(1)/tc(0)/bnksel(0) modck2/ap(2)/tc(1)/bnksel(1) modck3/ap(3)/tc(2)/bnksel(2) i ol = 3.2ma l_a14/par l_a15/frame /smi l_a16/trdy l_a17/irdy /ckstp_out l_a18/stop l_a19/devsel l_a20/idsel l_a21/perr l_a22/serr l_a23/req0 l_a24/req1 /hsejsw l_a25/gnt0 l_a26/gnt1 /hsled l_a27/gnt2 /hsenum l_a28/rst /core_sreset l_a29/inta l_a30/req2 l_a31 lcl_d(0-31)/ad(0-31) lcl_dp(0-3)/c/be (0-3) pa[0?31] pb[4?31] pc[0?31] pd[4?31] tdo v ol ?0.4 v table 3. dc electrical characteristics 1 (continued) characteristic symbol min max unit
mpc8250 hardware specifications, rev. 2 10 freescale semiconductor electrical and thermal characteristics 2.2 thermal characteristics table 4 describes thermal characteristics. 2.3 power considerations the average chip-junction temperature , t j , in c can be obtained from the following: t j = t a + (p d x ja ) (1) where t a = ambient temperature c ja = package thermal resistance , junction to ambient , c/w p d = p int + p i/o p int = i dd x v dd watts (chip internal power) p i/o = power dissipation on input and output pins (determined by user) for most applications p i/o < 0.3 x p int . if p i/o is neglected , an approximate relationship between p d and t j is the following: p d = k/(t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d x (t a + 273 c) + ja x p d 2 (3) 1 the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 2 the leakage current is measured for nominal vdd, vccsyn, and vdd. table 4. thermal characteristics characteristic symbol value unit air flow 480 tbga 516 pbga junction to ambient? single-layer board 1 1 assumes no thermal vias ja 13 24 c/w natural convection 10 18 1 m/s junction to ambient? four-layer board 11 16 natural convection 81 3 1 m / s junction to board 2 2 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. jb 48 c/w ? junction to case 3 3 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). jc 1.1 6 c/w ?
mpc8250 hardware specifications, rev. 2 freescale semiconductor 11 electrical and thermal characteristics where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k , the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . 2.3.1 layout practices each v cc pin should be provided with a low-impedance path to the board?s power supply. each ground pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc and ground should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the mpc8250 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize ove rdamped conditions and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems w ith higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. table 5 provides preliminary, estimated power dissipation for various configurations. note that suitable thermal management is required for conditions above p d = 3w (when the ambient temperature is 70 c or greater) to ensure the junction temperature does not exceed the maximum specified value. also note that the i/o power should be included when determining whether to use a heat sink. table 5. estimated power dissipation for various configurations 1 1 test temperature = room temperature (25 c) bus (mhz) cpm multiplier core cpu multiplier cpm (mhz) cpu (mhz) p int (w) 2 2 p int = i dd x v dd watts vddl 1.8 volts vddl 2.0 volts nominal maximum nominal maximum 66.66 2 3 133 200 1.2 2 1.8 2.3 66.66 2.5 3 166 200 1.3 2.1 1.9 2.3 66.66 3 4 200 266 ? ? 2.3 2.9 66.66 3 4.5 200 300 ? ? 2.4 3.1 83.33 2 3 166 250 ? ? 2.2 2.8 83.33 2 3 166 250 ? ? 2.2 2.8 83.33 2.5 3.5 208 291 ? ? 2.4 3.1
mpc8250 hardware specifications, rev. 2 12 freescale semiconductor electrical and thermal characteristics 2.4 ac electrical characteristics the following sections include illustrations and tables of clock diagrams, signals, and cpm outputs and inputs for the 66 mhz mpc8250 device. note that ac timings are based on a 50-p f load. typical output buffer impedances are shown in table 6 . table 7 lists cpm output characteristics. table 8 lists cpm input characteristics. table 6. output buffer impedances 1 1 these are typical values at 65 c. the impedance may vary by 25% with process and temperature. output buffers typical impedance ( ) 60x bus 40 local bus 40 memory controller 40 parallel i/o 46 pci 25 table 7. ac characteristics for cpm outputs 1 1 output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic max delay (ns) min delay (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp36a sp37a fcc outputs?internal clock (nmsi) 6 5.5 1 1 sp36b sp37b fcc outputs?external clock (nmsi) 14 12 2 1 sp40 sp41 tdm outputs/si 25 16 5 4 sp38a sp39a scc/smc/spi/i2c outputs?internal clock (nmsi) 19 16 1 0.5 sp38b sp39b ex_scc/smc/spi/i2c outputs?external clock (nmsi) 19 16 2 1 sp42 sp43 timer/idma outputs 14 11 1 0.5 sp42a sp43a pio outputs 14 11 0.5 0.5 table 8. ac characteristics for cpm inputs 1 spec number characteristic setup (ns) hold (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp16a sp17a fcc inputs?internal clock (nmsi) 10 8 0 0 sp16b sp17b fcc inputs?external clock (nmsi) 3 2.5 3 2
mpc8250 hardware specifications, rev. 2 freescale semiconductor 13 electrical and thermal characteristics note that although the specifications generally refere nce the rising edge of the clock, the following ac timing diagrams also apply when the falling edge is the active edge. figure 3 shows the fcc external clock. figure 3. fcc external clock diagram sp20 sp21 tdm inputs/si 15 12 12 10 sp18a sp19a scc/smc/spi/i2c inputs?internal clock (nmsi) 20 16 0 0 sp18b sp19b scc/smc/spi/i2c inputs?external clock (nmsi) 5 4 5 4 sp22 sp23 pio/timer/idma inputs 10 8 3 3 1 input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. table 8. ac characteristics for cpm inputs 1 spec number characteristic setup (ns) hold (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz serial clkin fcc input signals fcc output signals fcc output signals note : when gfmr[tci] = 1 note : when gfmr[tci] = 0 sp16b sp17b sp36b/sp37b sp36b/sp37b
mpc8250 hardware specifications, rev. 2 14 freescale semiconductor electrical and thermal characteristics figure 4 shows the fcc internal clock. figure 4. fcc internal clock diagram figure 5 shows the scc/smc/spi/i 2 c external clock. figure 5. scc/smc/spi/i 2 c external clock diagram brg_out fcc input signals fcc output signals fcc output signals note : when gfmr.tci = 1 note : when gfmr.tci = 0 sp36a/sp37a sp36a/sp37a sp17a sp16a serial clkin scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18b sp19b sp38b/sp39b (see note.) (see note.) note : there are four possible timing conditions for scc and spi: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge.
mpc8250 hardware specifications, rev. 2 freescale semiconductor 15 electrical and thermal characteristics figure 6 shows the scc/smc/spi/i 2 c internal clock. figure 6. scc/smc/spi/i 2 c internal clock diagram figure 7 shows tdm input and output signals. figure 7. tdm signal diagram brg_out scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18a sp19a sp38a/sp39a (see note.) (see note.) note : there are four possible timing conditions for scc and spi: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge. serial clkin tdm input signals tdm output signals sp20 sp21 sp40/sp41 note : there are four possible tdm timing conditions: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge.
mpc8250 hardware specifications, rev. 2 16 freescale semiconductor electrical and thermal characteristics figure 8 shows pio, timer, and dma signals. figure 8. pio, timer, and dma signal diagram table 9 lists siu input characteristics. table 9. ac characteristics for siu inputs 1 1 input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec number characteristic setup (ns) hold (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp11 sp10 aack /artry /ta /ts /tea /dbg /bg /br 650.50.5 sp12 sp10 data bus in normal mode 5 4 0.5 0.5 sp13 sp10 data bus in ecc and parity modes 8 6 0.5 0.5 sp14 sp10 dp pins 7 6 0.5 0.5 sp15 sp10 all other pins 5 4 0.5 0.5 sys clk pio/idma/timer[tgate assertion] input signals idma output signals sp22 sp23 sp42/sp43 timer(sp42/43)/ pio(sp42a/sp43a) sp42a/sp43a output signals sp42/sp43 timer input signal [tgate deassertion] sp22 sp23 note : tgate is asserted on the rising edge of the clock; it is deasserted on the falling edge. (see note) (see note)
mpc8250 hardware specifications, rev. 2 freescale semiconductor 17 electrical and thermal characteristics table 10 lists siu output characteristics. note activating data pi pelining (setting br x [dr] in the memory controller) improves the ac timing. when data pipelining is activated, sp12 can be used for data bus setup even when ecc or parity are used. also, sp33a can be used as the ac specification for dp signals. table 10. ac characteristics for siu outputs 1 1 output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic max delay (ns) min delay (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp31 sp30 psdval /tea /ta 760.50.5 sp32 sp30 add/add_atr./baddr/ci/gbl/wt 8 6.5 0.5 0.5 sp33a sp30 data bus 6.5 6.5 0.5 0.5 sp33b sp30 dp 8 7 0.5 0.5 sp34 sp30 memory controller signals/ale 6 5 0.5 0.5 sp35 sp30 all other signals 6 5.5 0.5 0.5
mpc8250 hardware specifications, rev. 2 18 freescale semiconductor electrical and thermal characteristics figure 9 shows the interaction of several bus signals. figure 9. bus signals figure 10 shows signal behavior for all parity modes (including ecc, rm w parity, and standard parity). figure 10. parity mode diagram clkin aack /artry /ta /ts /tea / data bus normal mode all other input signals psdval /tea /ta output signals add/add_atr/baddr/ci/ data bus output signals all other output signals sp11 sp12 sp15 sp10 sp10 sp10 sp30 sp30 sp30 sp30 sp32 sp33a sp35 dbg /bg /br input signals gbl/wt output signals sp31 input signal clkin data bus, ecc, and parity mode input signals dp mode input signal dp mode output signal sp13 sp10 sp14 sp10 sp33b/sp30
mpc8250 hardware specifications, rev. 2 freescale semiconductor 19 electrical and thermal characteristics figure 11 shows signal behavior in memc mode. figure 11. memc mode diagram note generally, all mpc8250 bus and system output signals are driven from the rising edge of the input clock (clkin). memory controller signals, however, trigger on four points within a clkin cycle. each cycle is divided by four internal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge, and t3 at the falling edge, of clkin. however, the spacing of t2 and t4 depends on the pll clock ratio selected, as shown in table 11 . figure 12 is a graphical representation of table 11 . figure 12. internal tick spacing for memory controller signals table 11. tick spacing for memory controller signals pll clock ratio tick spacing (t1 occurs at the rising edge of clkin) t2 t3 t4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 clkin 1/2 clkin 3/4 clkin 1:2.5 3/10 clkin 1/2 clkin 8/10 clkin 1:3.5 4/14 clkin 1/2 clkin 11/14 clkin clkin v_clk memory controller signals sp34/sp30 clkin t1 t2 t3 t4 clkin t1 t2 t3 t4 for 1:2.5 for 1:3.5 clkin t1 t2 t3 t4 for 1:2, 1:3, 1:4, 1:5, 1:6
mpc8250 hardware specifications, rev. 2 20 freescale semiconductor clock configuration modes note the upm machine outputs change on the internal tick determined by the memory controller programming; the ac specifications are relative to the internal tick. note that sdram and gpcm machine outputs change on clkin?s rising edge. 3 clock configuration modes the mpc8250 has three clocking modes: local, pci host, and pci agent. the clocking mode is set according to three input pins?pci_mode, pci_cfg[0], pci_modck?as shown in table 12 . in each clocking mode, the configuration of bus, core , pci, and cpm frequencie s is determined by seven bits during the power-up reset?three hardware configuration pins (modck[1?3]) and four bits from hardware configuration word[28?31] (modck_h). both the plls and the dividers are set according to the selected mpc8250 clock operation mode as described in the following sections. note clock configurations change only after por is asserted. 3.1 local bus mode table 13 shows the eight basic clock configurations for the mpc8250. another 49 configurations are available by using the configuration pin (rstconf ) and driving four pins on the data bus. table 12. mpc8250 clocking modes pins clocking mode pci clock frequency range (mhz) reference pci_mode pci_cfg[0] pci_modck 1 1 determines pci clock frequency range. refer to section 3.2, ?pci mode .? 1 ? ? local bus ? ta ble 1 3 and tab le 1 4 00 0 pci host 50?66 ta ble 1 5 and tab le 1 6 0 0 1 25?50 01 0 pci agent 50?66 ta ble 1 7 and tab le 1 8 0 1 1 25?50 table 13. clock default configurations modck[1?3] input clock frequency cpm multiplication factor cpm frequency core multiplication factor core frequency 000 33 mhz 3 100 mhz 4 133 mhz 001 33 mhz 3 100 mhz 5 166 mhz 010 33 mhz 4 133 mhz 4 133 mhz 011 33 mhz 4 133 mhz 5 166 mhz
mpc8250 hardware specifications, rev. 2 freescale semiconductor 21 clock configuration modes table 14 describes all possible clock configurations when using the hard reset configuration sequence. note also that basic modes are shown in boldface type. the frequencies listed are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user?s device. 100 66 mhz 2 133 mhz 2.5 166 mhz 101 66 mhz 2 133 mhz 3 200 mhz 110 66 mhz 2.5 166 mhz 2.5 166 mhz 111 66 mhz 2.5 166 mhz 3 200 mhz table 14. clock configuration modes 1 modck_h?modck[1?3] input clock frequency 2, 3 cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2 0001_000 33 mhz 2 66 mhz 4 133 mhz 0001_001 33 mhz 2 66 mhz 5 166 mhz 0001_010 33 mhz 2 66 mhz 6 200 mhz 0001_011 33 mhz 2 66 mhz 7 233 mhz 0001_100 33 mhz 2 66 mhz 8 266 mhz 0001_101 33 mhz 3 100 mhz 4 133 mhz 0001_110 33 mhz 3 100 mhz 5 166 mhz 0001_111 33 mhz 3 100 mhz 6 200 mhz 0010_000 33 mhz 3 100 mhz 7 233 mhz 0010_001 33 mhz 3 100 mhz 8 266 mhz 0010_010 33 mhz 4 133 mhz 4 133 mhz 0010_011 33 mhz 4 133 mhz 5 166 mhz 0010_100 33 mhz 4 133 mhz 6 200 mhz 0010_101 33 mhz 4 133 mhz 7 233 mhz 0010_110 33 mhz 4 133 mhz 8 266 mhz 0010_111 33 mhz 5 166 mhz 4 133 mhz 0011_000 33 mhz 5 166 mhz 5 166 mhz 0011_001 33 mhz 5 166 mhz 6 200 mhz 0011_010 33 mhz 5 166 mhz 7 233 mhz 0011_011 33 mhz 5 166 mhz 8 266 mhz table 13. clock default configurations modck[1?3] input clock frequency cpm multiplication factor cpm frequency core multiplication factor core frequency
mpc8250 hardware specifications, rev. 2 22 freescale semiconductor clock configuration modes 0011_100 33 mhz 6 200 mhz 4 133 mhz 0011_101 33 mhz 6 200 mhz 5 166 mhz 0011_110 33 mhz 6 200 mhz 6 200 mhz 0011_111 33 mhz 6 200 mhz 7 233 mhz 0100_000 33 mhz 6 200 mhz 8 266 mhz 0100_001 reserved 0100_010 0100_011 0100_100 0100_101 0100_110 0100_111 reserved 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 mhz 2 133 mhz 2 133 mhz 0101_110 66 mhz 2 133 mhz 2.5 166 mhz 0101_111 66 mhz 2 133 mhz 3 200 mhz 0110_000 66 mhz 2 133 mhz 3.5 233 mhz 0110_001 66 mhz 2 133 mhz 4 266 mhz 0110_010 66 mhz 2 133 mhz 4.5 300 mhz 0110_011 66 mhz 2.5 166 mhz 2 133 mhz 0110_100 66 mhz 2.5 166 mhz 2.5 166 mhz 0110_101 66 mhz 2.5 166 mhz 3 200 mhz 0110_110 66 mhz 2.5 166 mhz 3.5 233 mhz 0110_111 66 mhz 2.5 166 mhz 4 266 mhz 0111_000 66 mhz 2.5 166 mhz 4.5 300 mhz table 14. clock configuration modes 1 (continued) modck_h?modck[1?3] input clock frequency 2, 3 cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2
mpc8250 hardware specifications, rev. 2 freescale semiconductor 23 clock configuration modes 3.2 pci mode the pci mode is selected according to three input pins, as shown in table 12 . in addition, note the following: note: pci_modck in pci mode only, pci_modck comes from the lgpl5 pin and modck_h[0?3] comes from {lgpl0, lgpl1, lgpl2, lgpl3}. note: tval (output hold) the minimum tval = 2 when pci_modck = 1, and the minimum tval = 1 when pci_modck = 0. therefore, designers should use clock configurations that fit this condition to achieve pci-compliant ac timing. note clock configurations change only after por is asserted. 0111_001 66 mhz 3 200 mhz 2 133 mhz 0111_010 66 mhz 3 200 mhz 2.5 166 mhz 0111_011 66 mhz 3 200 mhz 3 200 mhz 0111_100 66 mhz 3 200 mhz 3.5 233 mhz 0111_101 66 mhz 3 200 mhz 4 266 mhz 0111_110 66 mhz 3 200 mhz 4.5 300 mhz 0111_111 66 mhz 3.5 233 mhz 2 133 mhz 1000_000 66 mhz 3.5 233 mhz 2.5 166 mhz 1000_001 66 mhz 3.5 233 mhz 3 200 mhz 1000_010 66 mhz 3.5 233 mhz 3.5 233 mhz 1000_011 66 mhz 3.5 233 mhz 4 266 mhz 1000_100 66 mhz 3.5 233 mhz 4.5 300 mhz 1 because of speed dependencies, not all of the possible configurations in table 14 are applicable. 2 the user should choose the input clock frequency and the multiplication factors such that the frequency of the cpu is equal to or greater than 133 mhz (150 mhz for extended temperature parts) and the cpm ranges between 66?233 mhz. 3 input clock frequency is given only for the purpose of reference. user should set modck_h?modck_l so that the resulting configuration does not exceed the frequency rating of the user?s part. table 14. clock configuration modes 1 (continued) modck_h?modck[1?3] input clock frequency 2, 3 cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2
mpc8250 hardware specifications, rev. 2 24 freescale semiconductor clock configuration modes 3.2.1 pci host mode the frequencies listed in table 15 are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configurati on does not exceed the frequency rating of the user?s device. table 16 describes all possible clock configurations when using the mpc8250?s internal pci bridge in host mode. table 15. clock default configurations in pci host mode (modck_hi = 0000) modck[1?3] 1 1 assumes modck_hi = 0000. input clock frequency (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor 2 2 the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) refer to ta b l e 1 2 . pci frequency 2 000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 001 66 mhz 2 133 mhz 3 200 mhz 2/4 66/33 mhz 010 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 011 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 100 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 101 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz 110 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 111 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz table 16. clock configuration modes in pci host mode modck_h ? modck[1? 3] input clock frequency 1 (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor 2 pci frequency 2 0001_000 33 mhz 3 100 mhz 5 166 mhz 3/6 33/16 mhz 0001_001 33 mhz 3 100 mhz 6 200 mhz 3/6 33/16 mhz 0001_010 33 mhz 3 100 mhz 7 233 mhz 3/6 33/16 mhz 0001_011 33 mhz 3 100 mhz 8 266 mhz 3/6 33/16 mhz 0010_000 33 mhz 4 133 mhz 5 166 mhz 4/8 33 /16 mhz 0010_001 33 mhz 4 133 mhz 6 200 mhz 4/8 33/16 mhz 0010_010 33 mhz 4 133 mhz 7 233 mhz 4/8 33/16 mhz 0010_011 33 mhz 4 133 mhz 8 266 mhz 4/8 33/16 mhz 0011_000 3 33 mhz 5 166 mhz 5 166 mhz 5 33 mhz 0011_001 3 33 mhz 5 166 mhz 6 200 mhz 5 33 mhz
mpc8250 hardware specifications, rev. 2 freescale semiconductor 25 clock configuration modes 0011_010 3 33 mhz 5 166 mhz 7 233 mhz 5 33 mhz 0011_011 3 33 mhz 5 166 mhz 8 266 mhz 5 33 mhz 0100_000 3 33 mhz 6 200 mhz 5 166 mhz 6 33 mhz 0100_001 3 33 mhz 6 200 mhz 6 200 mhz 6 33 mhz 0100_010 3 33 mhz 6 200 mhz 7 233 mhz 6 33 mhz 0100_011 3 33 mhz 6 200 mhz 8 266 mhz 6 33 mhz 0101_000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 0101_001 66 mhz 2 133 mhz 3 200 mhz 2 /4 66 /33 mhz 0101_010 66 mhz 2 133 mhz 3.5 233 mhz 2/4 66/33 mhz 0101_011 66 mhz 2 133 mhz 4 266 mhz 2/4 66/33 mhz 0101_100 66 mhz 2 133 mhz 4.5 300 mhz 2/4 66/33 mhz 0110_000 66 mhz 2.5 166 mhz 2.5 166 mhz 3/6 55/28 mhz 0110_001 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 0110_010 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 0110_011 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 0110_100 66 mhz 2.5 166 mhz 4.5 300 mhz 3/6 55/28 mhz 0111_000 66 mhz 3 200 mhz 2.5 166 mhz 3/6 66/33 mhz 0111_001 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz 0111_010 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 0111_011 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz 0111_100 66 mhz 3 200 mhz 4.5 300 mhz 3/6 66/33 mhz 1000_000 66 mhz 3 200 mhz 2.5 166 mhz 4/8 50/25 mhz 1000_001 66 mhz 3 200 mhz 3 200 mhz 4/8 50/25 mhz 1000_010 66 mhz 3 200 mhz 3.5 233 mhz 4/8 50/25 mhz 1000_011 66 mhz 3 200 mhz 4 266 mhz 4/8 50/25 mhz 1000_100 66 mhz 3 200 mhz 4.5 300 mhz 4/8 50/25 mhz 1001_000 66 mhz 3.5 233 mhz 2.5 166 mhz 4/8 58/29 mhz table 16. clock configuration modes in pci host mode (continued) modck_h ? modck[1? 3] input clock frequency 1 (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor 2 pci frequency 2
mpc8250 hardware specifications, rev. 2 26 freescale semiconductor clock configuration modes 3.2.2 pci agent mode the frequencies listed in table 17 are for the purpose of illustration only. users must select a mode and input bus frequency so that the resulting configurati on does not exceed the frequency rating of the user?s device. 1001_001 66 mhz 3.5 233 mhz 3 200 mhz 4/8 58/29 mhz 1001_010 66 mhz 3.5 233 mhz 3.5 233 mhz 4/8 58/29 mhz 1001_011 66 mhz 3.5 233 mhz 4 266 mhz 4/8 58/29 mhz 1001_100 66 mhz 3.5 233 mhz 4.5 300 mhz 4/8 58/29 mhz 1010_000 100 mhz 2 200 mhz 2 200 mhz 3/6 66/33 mhz 1010_001 100 mhz 2 200 mhz 2.5 250 mhz 3/6 66/33 mhz 1010_010 100 mhz 2 200 mhz 3 300 mhz 3/6 66/33 mhz 1010_011 100 mhz 2 200 mhz 3.5 350 mhz 3/6 66/33 mhz 1010_100 100 mhz 2 200 mhz 4 400 mhz 3/6 66/33 mhz 1011_000 100 mhz 2.5 250 mhz 2 200 mhz 4/8 62/31 mhz 1011_001 100 mhz 2.5 250 mhz 2.5 250 mhz 4/8 62/31mhz 1011_010 100 mhz 2.5 250 mhz 3 300 mhz 4/8 62/31 mhz 1011_011 100 mhz 2.5 250 mhz 3.5 350 mhz 4/8 62/31 mhz 1011_100 100 mhz 2.5 250 mhz 4 400 mhz 4/8 62/31 mhz 1 input clock frequency is given only for the purpose of reference. user should set modck_h?modck_l so that the resulting configuration does not exceed the frequency rating of the user?s part. 2 the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.). refer to tab le 1 2 3 in this mode, pci_modck must be ?0?. table 17. clock default configurations in pci agent mode (modck_hi = 0000) modck[1?3] 1 input clock frequency (pci) 2 cpm multiplication factor 2 cpm frequency core multiplication factor core frequency 3 bus division factor 60x bus frequency 4 000 66/33 mhz 2/4 133 mhz 2.5 166 mhz 2 66 mhz 001 66/33 mhz 2/4 133 mhz 3 200 mhz 2 66 mhz 010 66/33 mhz 3/6 200 mhz 3 200 mhz 3 66 mhz 011 66/33 mhz 3/6 200 mhz 4 266 mhz 3 66 mhz table 16. clock configuration modes in pci host mode (continued) modck_h ? modck[1? 3] input clock frequency 1 (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor 2 pci frequency 2
mpc8250 hardware specifications, rev. 2 freescale semiconductor 27 clock configuration modes table 18 describes all possible clock configurations when using the mpc8250?s internal pci bridge in agent mode. 100 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 101 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 110 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 111 66/33 mhz 4/8 266 mhz 3 300 mhz 2.5 100 mhz 1 assumes modck_hi = 0000. 2 the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2. refer to ta ble 1 2 3 core frequency = (60x bus frequency)(core multiplication factor) 4 bus frequency = cpm frequency / bus division factor table 18. clock configuration modes in pci agent mode modck_h ? modck[1? 3] input clock frequency (pci) 1, 2 cpm multiplication factor 1 cpm frequency core multiplication factor core frequency 3 bus division factor 60x bus frequency 4 0001_001 66/33 mhz 2/4 133 mhz 5 166 mhz 4 33 mhz 0001_010 66/33 mhz 2/4 133 mhz 6 200 mhz 4 33 mhz 0001_011 66/33 mhz 2/4 133 mhz 7 233 mhz 4 33 mhz 0001_100 66/33 mhz 2/4 133 mhz 8 266 mhz 4 33 mhz 0010_001 50/25 mhz 3/6 150 mhz 3 180 mhz 2.5 60 mhz 0010_010 50/25 mhz 3/6 150 mhz 3.5 210 mhz 2.5 60 mhz 0010_011 50/25 mhz 3/6 150 mhz 4 240 mhz 2.5 60 mhz 0010_100 50/25 mhz 3/6 150 mhz 4.5 270 mhz 2.5 60 mhz 0011_000 66/33 mhz 2/4 133 mhz 2.5 110mhz 3 44 mhz 0011_001 66/33 mhz 2/4 133 mhz 3 132 mhz 3 44 mhz 0011_010 66/33 mhz 2/4 133 mhz 3.5 154 mhz 3 44 mhz 0011_011 66/33 mhz 2/4 133 mhz 4 176mhz 3 44 mhz 0011_100 66/33 mhz 2/4 133 mhz 4.5 198 mhz 3 44 mhz 0100_000 66/33 mhz 3/6 200 mhz 2.5 166 mhz 3 66 mhz 0100_001 66/33 mhz 3/6 200 mhz 3 200 mhz 366 mhz 0100_010 66/33 mhz 3/6 200 mhz 3.5 233 mhz 366 mhz table 17. clock default configurations in pci agent mode (modck_hi = 0000) modck[1?3] 1 input clock frequency (pci) 2 cpm multiplication factor 2 cpm frequency core multiplication factor core frequency 3 bus division factor 60x bus frequency 4
mpc8250 hardware specifications, rev. 2 28 freescale semiconductor clock configuration modes 0100_011 66/33 mhz 3/6 200 mhz 4 266 mhz 366 mhz 0100_100 66/33 mhz 3/6 200 mhz 4.5 300 mhz 366 mhz 0101_000 5 33 mhz 5 166 mhz 2.5 166 mhz 2.5 66 mhz 0101_001 5 33 mhz 5 166 mhz 3 200 mhz 2.5 66 mhz 0101_010 5 33 mhz 5 166 mhz 3.5 233 mhz 2.5 66 mhz 0101_011 5 33 mhz 5 166 mhz 4 266 mhz 2.5 66 mhz 0101_100 5 33 mhz 5 166 mhz 4.5 300 mhz 2.5 66 mhz 0110_000 50/25 mhz 4/8 200 mhz 2.5 166 mhz 3 66 mhz 0110_001 50/25 mhz 4/8 200 mhz 3 200 mhz 3 66 mhz 0110_010 50/25 mhz 4/8 200 mhz 3.5 233 mhz 3 66 mhz 0110_011 50/25 mhz 4/8 200 mhz 4 266 mhz 3 66 mhz 0110_100 50/25 mhz 4/8 200 mhz 4.5 300 mhz 3 66 mhz 0111_000 66/33 mhz 3/6 200 mhz 2 200 mhz 2 100 mhz 0111_001 66/33 mhz 3/6 200 mhz 2.5 250 mhz 2 100 mhz 0111_010 66/33 mhz 3/6 200 mhz 3 300 mhz 2 100 mhz 0111_011 66/33 mhz 3/6 200 mhz 3.5 350 mhz 2 100 mhz 1000_000 66/33 mhz 3/6 200 mhz 2 160 mhz 2.5 80 mhz 1000_001 66/33 mhz 3/6 200 mhz 2.5 200 mhz 2.5 80 mhz 1000_010 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 1000_011 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 1000_100 66/33 mhz 3/6 200 mhz 4 320 mhz 2.5 80 mhz 1000_101 66/33 mhz 3/6 200 mhz 4.5 360 mhz 2.5 80 mhz 1001_000 66/33 mhz 4/8 266 mhz 2.5 166 mhz 4 66 mhz 1001_001 66/33 mhz 4/8 266 mhz 3 200 mhz 4 66 mhz 1001_010 66/33 mhz 4/8 266 mhz 3.5 233 mhz 4 66 mhz 1001_011 66/33 mhz 4/8 266 mhz 4 266 mhz 4 66 mhz 1001_100 66/33 mhz 4/8 266 mhz 4.5 300 mhz 4 66 mhz table 18. clock configuration modes in pci agent mode (continued) modck_h ? modck[1? 3] input clock frequency (pci) 1, 2 cpm multiplication factor 1 cpm frequency core multiplication factor core frequency 3 bus division factor 60x bus frequency 4
mpc8250 hardware specifications, rev. 2 freescale semiconductor 29 pinout 4 pinout this section provides the pin assignments and pinout list for the mpc8250. 4.1 tbga package the following figures and table represent the standard 480 tbga package. for information on the alternate package, refer to section 4.2, ?pbga package.? 1010_000 66/33 mhz 4/8 266 mhz 2.5 222 mhz 3 88 mhz 1010_001 66/33 mhz 4/8 266 mhz 3 266 mhz 3 88 mhz 1010_010 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 1010_011 66/33 mhz 4/8 266 mhz 4 350 mhz 3 88 mhz 1010_100 66/33 mhz 4/8 266 mhz 4.5 400 mhz 3 88 mhz 1011_000 66/33 mhz 4/8 266 mhz 2 212mhz 2.5 106 mhz 1011_001 66/33 mhz 4/8 266 mhz 2.5 265 mhz 2.5 106 mhz 1011_010 66/33 mhz 4/8 266 mhz 3 318 mhz 2.5 106 mhz 1011_011 66/33 mhz 4/8 266 mhz 3.5 371 mhz 2.5 106 mhz 1011_100 66/33 mhz 4/8 266 mhz 4 424 mhz 2.5 106 mhz 1 the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2. refer to ta b l e 1 2 2 input clock frequency is given only for the purpose of reference. user should set modck_h?modck_l so that the resulting configuration does not exceed the frequency rating of the user?s part. 3 core frequency = (60x bus frequency)(core multiplication factor) 4 bus frequency = cpm frequency / bus division factor 5 in this mode, pci_modck must be ?1?. table 18. clock configuration modes in pci agent mode (continued) modck_h ? modck[1? 3] input clock frequency (pci) 1, 2 cpm multiplication factor 1 cpm frequency core multiplication factor core frequency 3 bus division factor 60x bus frequency 4
mpc8250 hardware specifications, rev. 2 30 freescale semiconductor pinout 4.1.1 tbga pin assignments figure 13 shows the pinout of the tbga packag e as viewed from the top surface. figure 13. pinout of the 480 tbga package as viewed from the top surface 1 2 3 4 5 6 7 8 910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 not to scale 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj
mpc8250 hardware specifications, rev. 2 freescale semiconductor 31 pinout figure 14 shows the side profile of the tbga package to indicate the direction of the top surface view. figure 14. side view of the tbga package table 20 shows the pinout list of the tbga package of the mpc8250. table 19 defines the conventions and acronyms used in table 20 . table 19. symbol legend symbol meaning overbar signals with overbars, such as ta , are active low. mii indicates that a signal is part of the media independent interface. table 20. mpc8250 tbga package pinout list pin name ball br w5 bg f4 abb/irq2 e2 ts e3 a0 g1 a1 h5 a2 h2 a3 h1 a4 j5 a5 j4 a6 j3 a7 j2 a8 j1 a9 k4 a10 k3 a11 k2 a12 k1 soldermask copper traces die copper heat spreader (oxidized for insulation) 1.27 mm pitch glob-top dam wire bonds etched pressure sensitive die glob-top filled area polymide tape cavity adhesive attach view
mpc8250 hardware specifications, rev. 2 32 freescale semiconductor pinout a13 l5 a14 l4 a15 l3 a16 l2 a17 l1 a18 m5 a19 n5 a20 n4 a21 n3 a22 n2 a23 n1 a24 p4 a25 p3 a26 p2 a27 p1 a28 r1 a29 r3 a30 r5 a31 r4 tt0 f1 tt1 g4 tt2 g3 tt3 g2 tt4 f2 tbst d3 tsiz0 c1 tsiz1 e4 tsiz2 d2 tsiz3 f5 aack f3 artry e1 dbg v1 dbb/irq3 v2 d0 b20 d1 a18 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 33 pinout d2 a16 d3 a13 d4 e12 d5 d9 d6 a6 d7 b5 d8 a20 d9 e17 d10 b15 d11 b13 d12 a11 d13 e9 d14 b7 d15 b4 d16 d19 d17 d17 d18 d15 d19 c13 d20 b11 d21 a8 d22 a5 d23 c5 d24 c19 d25 c17 d26 c15 d27 d13 d28 c11 d29 b8 d30 a4 d31 e6 d32 e18 d33 b17 d34 a15 d35 a12 d36 d11 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 34 freescale semiconductor pinout d37 c8 d38 e7 d39 a3 d40 d18 d41 a17 d42 a14 d43 b12 d44 a10 d45 d8 d46 b6 d47 c4 d48 c18 d49 e16 d50 b14 d51 c12 d52 b10 d53 a7 d54 c6 d55 d5 d56 b18 d57 b16 d58 e14 d59 d12 d60 c10 d61 e8 d62 d6 d63 c2 dp0/rsrv /ext_br2 b22 irq1 /dp1/ext_bg2 a22 irq2 /dp2/tlbisync /ext_dbg2 e21 irq3 /dp3/ckstp_out /ext_br3 d21 irq4 /dp4/core_sreset /ext_bg3 c21 irq5 /dp5/tben /ext_dbg3 b21 irq6 /dp6/cse0 a21 irq7 /dp7/cse1 e20 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 35 pinout psdval v3 ta c22 tea v5 gbl/irq1 w1 ci /baddr29/irq2 u2 wt /baddr30/irq3 u3 l2_hit/irq4 y4 cpu_bg /baddr31/irq5 u4 cpu_dbg r2 cpu_br y3 cs0 f25 cs1 c29 cs2 e27 cs3 e28 cs4 f26 cs5 f27 cs6 f28 cs7 g25 cs8 d29 cs9 e29 cs10 /bctl1 f29 cs11 /ap0 g28 baddr27 t5 baddr28 u1 ale t2 bctl0 a27 pwe0/psddqm0/pbs0 c25 pwe1/psddqm1/pbs1 e24 pwe2/psddqm2/pbs2 d24 pwe3/psddqm3/pbs3 c24 pwe4/psddqm4/pbs4 b26 pwe5/psddqm5/pbs5 a26 pwe6/psddqm6/pbs6 b25 pwe7/psddqm7/pbs7 a25 psda10/pgpl0 e23 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 36 freescale semiconductor pinout psdwe /pgpl1 b24 poe /psdras /pgpl2 a24 psdcas /pgpl3 b23 pgta /pupmwait/pgpl4/ppbs a23 psdamux/pgpl5 d22 lwe0/lsddqm0/lbs0 /pci_cfg0 h28 lwe1/lsddqm1/lbs1/pci_cfg1 h27 lwe2/lsddqm2/lbs2/pci_cfg2 h26 lwe3/lsddqm3/lbs3/pci_cfg3 g29 lsda10/lgpl0/pci_modckh0 d27 lsdwe /lgpl1/pci_modckh1 c28 loe /lsdras /lgpl2/pci_modckh2 e26 lsdcas /lgpl3/pci_modckh3 d25 lgta /lupmwait/lgpl4/lpbs c26 lgpl5/lsdamux/pci_modck b27 lwr d28 l_a14/par n27 l_a15/frame /smi t29 l_a16/trdy r27 l_a17/irdy /ckstp_out r26 l_a18/stop r29 l_a19/devsel r28 l_a20/idsel w29 l_a21/perr p28 l_a22/serr n26 l_a23/req0 aa27 l_a24/req1 /hsejsw p29 l_a25/gnt0 aa26 l_a26/gnt1 /hsled n25 l_a27/gnt2 /hsenum aa25 l_a28/rst /core_sreset ab29 l_a29/inta ab28 l_a30/req2 p25 l_a31/dllout ab27 lcl_d0/ad0 h29 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 37 pinout lcl_d1/ad1 j29 lcl_d2/ad2 j28 lcl_d3/ad3 j27 lcl_d4/ad4 j26 lcl_d5/ad5 j25 lcl_d6/ad6 k25 lcl_d7/ad7 l29 lcl_d8/ad8 l27 lcl_d9/ad9 l26 lcl_d10/ad10 l25 lcl_d11/ad11 m29 lcl_d12/ad12 m28 lcl_d13/ad13 m27 lcl_d14/ad14 m26 lcl_d15/ad15 n29 lcl_d16/ad16 t25 lcl_d17/ad17 u27 lcl_d18/ad18 u26 lcl_d19/ad19 u25 lcl_d20/ad20 v29 lcl_d21/ad21 v28 lcl_d22/ad22 v27 lcl_d23/ad23 v26 lcl_d24/ad24 w27 lcl_d25/ad25 w26 lcl_d26/ad26 w25 lcl_d27/ad27 y29 lcl_d28/ad28 y28 lcl_d29/ad29 y25 lcl_d30/ad30 aa29 lcl_d31/ad31 aa28 lcl_dp0/c0/be0 l28 lcl_dp1/c1/be1 n28 lcl_dp2/c2/be2 t28 lcl_dp3/c3/be3 w28 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 38 freescale semiconductor pinout irq0/nmi_out t1 irq7/int_out/ape d1 trst ah3 tck ag5 tms aj3 tdi ae6 tdo af5 tris ab4 poreset ag6 hreset ah5 sreset af6 qreq aa3 rstconf aj4 modck1/ap1/tc0/bnksel0 w2 modck2/ap2/tc1/bnksel1 w3 modck3/ap3/tc2/bnksel2 w4 xfc ab2 clkin1 ah4 pa0/restart1 /dreq3 ac29 1 pa1/reject1 /done3 ac25 1 pa2/clk20/dack3 ae28 1 pa3/clk19/dack4 /l1rxd1a2 ag29 1 pa4/reject2 /done4 ag28 1 pa5/restart2 /dreq4 ag26 1 pa 6 ae24 1 pa7/smsyn2 ah25 1 pa8/smrxd2 af23 1 pa 9 / s m t x d 2 ah23 1 pa10/msnum5 ae22 1 pa11/msnum4 ah22 1 pa12/msnum3 aj21 1 pa13/msnum2 ah20 1 pa14/fcc1_rxd3 ag19 1 pa15/fcc1_rxd2 af18 1 pa16/fcc1_rxd1 af17 1 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 39 pinout pa17/fcc1_rxd0/fcc1_rxd ae16 1 pa18/fcc1_txd0/fcc1_txd aj16 1 pa19/fcc1_txd1 ag15 1 pa20/fcc1_txd2 aj13 1 pa21/fcc1_txd3 ae13 1 pa 2 2 af12 1 pa 2 3 ag11 1 pa24/msnum1 ah9 1 pa25/msnum0 aj8 1 pa26/fcc1_mii_rx_er ah7 1 pa27/fcc1_mii_rx_dv af7 1 pa28/fcc1_mii_tx_en ad5 1 pa29/fcc1_mii_tx_er af1 1 pa30/fcc1_mii_crs/fcc1_rts ad3 1 pa31/fcc1_mii_col ab5 1 pb4/fcc3_txd3/l1rsynca2/fcc3_rts ad28 1 pb5/fcc3_txd2/l1tsynca2/l1gnta2 ad26 1 pb6/fcc3_txd1/l1rxda2/l1rxd0a2 ad25 1 pb7/fcc3_txd0/fcc3_txd/l1txda2/l1txd0a2 ae26 1 pb8/fcc3_rxd0/fcc3_rxd/txd3 ah27 1 pb9/fcc3_rxd1/l1txd2a2 ag24 1 pb10/fcc3_rxd2 ah24 1 pb11/fcc3_rxd3 aj24 1 pb12/fcc3_mii_crs/txd2 ag22 1 pb13/fcc3_mii_col/l1txd1a2 ah21 1 pb14/fcc3_mii_tx_en/rxd3 ag20 1 pb15/fcc3_mii_tx_er/rxd2 af19 1 pb16/fcc3_mii_rx_er/clk18 aj18 1 pb17/fcc3_mii_rx_dv/clk17 aj17 1 pb18/fcc2_rxd3/l1clkod2/l1rxd2a2 ae14 1 pb19/fcc2_rxd2/l1rqd2/l1rxd3a2 af13 1 pb20/fcc2_rxd1/l1rsyncd2/l1txd1a1 ag12 1 pb21/fcc2_rxd0/fcc2_rxd/l1tsyncd2/l1gntd2 ah11 1 pb22/fcc2_txd0/fcc2_txd/l1rxdd2 ah16 1 pb23/fcc2_txd1/l1txdd2 ae15 1 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 40 freescale semiconductor pinout pb24/fcc2_txd2/l1rsyncc2 aj9 1 pb25/fcc2_txd3/l1tsyncc2/l1gntc2 ae9 1 pb26/fcc2_mii_crs/l1rxdc2 aj7 1 pb27/fcc2_mii_col/l1txdc2 ah6 1 pb28/fcc2_mii_rx_er/fcc2_rts /l1tsyncb2/l1gntb2/txd1 ae3 1 pb29/l1rsyncb2/fcc2_mii_tx_en ae2 1 pb30/fcc2_mii_rx_dv/l1rxdb2 ac5 1 pb31/fcc2_mii_tx_er/l1txdb2 ac4 1 pc0/dreq1/brgo7/smsyn2 /l1clkoa2 ab26 1 pc1/dreq2/brgo6/l1rqa2 ad29 1 pc2/fcc3_cd /done2 ae29 1 pc3/fcc3_cts /dack2 /cts4 ae27 1 pc4/si2_l1st4/fcc2_cd af27 1 pc5/si2_l1st3/fcc2_cts af24 1 pc6/fcc1_cd aj26 1 pc7/fcc1_cts aj25 1 pc8/cd4 /rena4/si2_l1st2/cts3 af22 1 pc9/cts4 /clsn4/si2_l1st1/l1tsynca2/l1gnta2 ae21 1 pc10/cd3 /rena3 af20 1 pc11/cts3 /clsn3/l1txd3a2 ae19 1 pc12/cd2 /rena2 ae18 1 pc13/cts2 /clsn2 ah18 1 pc14/cd1 /rena1 ah17 1 pc15/cts1 /clsn1/smtxd2 ag16 1 pc16/clk16/tin4 af15 1 pc17/clk15/tin3/brgo8 aj15 1 pc18/clk14/tgate2 ah14 1 pc19/clk13/brgo7/spiclk ag13 1 pc20/clk12/tgate1 ah12 1 pc21/clk11/brgo6 aj11 1 pc22/clk10/done1 ag10 1 pc23/clk9/brgo5/dack1 ae10 1 pc24/clk8/tout4 af9 1 pc25/clk7/brgo4 ae8 1 pc26/clk6/tout3 /tmclk aj6 1 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 41 pinout pc27/fcc3_txd/fcc3_txd0/clk5/brgo3 ag2 1 pc28/clk4/tin1/tout2 /cts2 /clsn2 af3 1 pc29/clk3/tin2/brgo2/cts1 /clsn1 af2 1 pc30/clk2/tout1 ae1 1 pc31/clk1/brgo1 ad1 1 pd4/brgo8/fcc3_rts /smrxd2 ac28 1 pd5/done1 ad27 1 pd6/dack1 af29 1 pd7/smsyn1fcc1_txclav2 af28 1 pd8/smrxd1/brgo5 ag25 1 pd9/smtxd1/brgo3 ah26 1 pd10/l1clkob2/brgo4 aj27 1 pd11/l1rqb2 aj23 1 pd12 ag23 1 pd13 aj22 1 pd14/l1clkoc2/i2cscl ae20 1 pd15/l1rqc2 /i2csda aj20 1 pd16/spimiso ag18 1 pd17/brgo2/spimosi ag17 1 pd18/spiclk af16 1 pd19/spisel/brgo ah15 1 pd20/rts4 /tena4/l1rsynca2 aj14 1 pd21/txd4/l1rxd0a2/l1rxda2 ah13 1 pd22/rxd4/l1txd0a2/l1txda2 aj12 1 pd23/rts3 /tena3 ae12 1 pd24/txd3 af10 1 pd25/rxd3 ag9 1 pd26/rts2 /tena2 ah8 1 pd27/txd2 ag7 1 pd28/rxd2 ae4 1 pd29/rts1 /tena1 ag1 1 pd30/txd1 ad4 1 pd31/rxd1 ad2 1 vccsyn ab3 vccsyn1 b9 table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 42 freescale semiconductor pinout 4.2 pbga package the following figures and table represent the alternate 516 pbga package. for information on the standard package for the mpc8250, refer to section 4.1, ?tbga package.? gndsyn ab1 clkin2 ae11 spare4 2 u5 pci_mode 3 af25 spare6 2 v4 thermal0 4 aa1 thermal1 4 ag4 i/o power ag21, ag14, ag8, aj1, aj2, ah1, ah2, ag3, af4, ae5, ac27, y27, t27, p27, k26, g27, ae25, af26, ag27, ah28, ah29, aj28, aj29, c7, c14, c16, c20, c23, e10, a28, a29, b28, b29, c27, d26, e25, h3, m4, t3, aa4, a1, a2, b1, b2, c3, d4, e5 core power u28, u29, k28, k29, a9, a19, b19, m1, m2, y1, y2, ac1, ac2, ah19, aj19, ah10, aj10, aj5 ground aa5, af21, af14, af8, ae7, af11, ae17, ae23, ac26, ab25, y26, v25, t26, r25, p26, m25, k27, h25, g26, d7, d10, d14, d16, d20, d23, c9, e11, e13, e15, e19, e22, b3, g5, h4, k5, m3, p5, t4, y5, aa2, ac3 1 the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 2 must be pulled down or left floating. 3 if pci is not desired, this pin should be pulled up or left floating. 4 for information on how to use this pin, refer to mpc8260 powerquicc ii thermal resistor guide (an2271/d) available at www.freescale.com. table 20. mpc8250 tbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 43 pinout 4.2.1 pbga pin assignments figure 15 shows the pinout of the pbga package as viewed from the top surface. figure 15. pinout of the 516 pbga package (view from top) 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 not to scale 1234567891011121314151617181920212223242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
mpc8250 hardware specifications, rev. 2 44 freescale semiconductor pinout figure 16 shows the side profile of the pbga package to indicate the direction of the top surface view. figure 16. side view of the pbga package table 22 shows the pinout list of the pbga package of the mpc8250. table 21 defines conventions and acronyms used in table 22 . table 21. symbol legend symbol meaning overbar signals with overbars, such as ta , are active low. mii indicates that a signal is part of the media independent interface. table 22. mpc8250 pbga package pinout list pin name ball br c16 bg d2 abb/irq2 c1 ts d1 a0 d5 a1 e8 a2 c4 a3 b4 a4 a4 a5 d7 a6 d8 a7 c6 a8 b5 a9 b6 a10 c7 a11 c8 a12 a6 a13 d9 die transfer molding compound 1 mm pitch wire bonds attach die ball bond screen-printed solder mask cu substrate traces bt resin glass epoxy plated substrate via
mpc8250 hardware specifications, rev. 2 freescale semiconductor 45 pinout a14 f11 a15 b7 a16 b8 a17 c9 a18 a7 a19 b9 a20 e11 a21 a8 a22 d11 a23 b10 a24 c11 a25 a9 a26 b11 a27 c12 a28 d12 a29 a10 a30 b12 a31 b13 tt0 e7 tt1 b3 tt2 f8 tt3 a3 tt4 c3 tbst f5 tsiz0 e3 tsiz1 e2 tsiz2 e1 tsiz3 e4 aack d3 artry c2 dbg a14 dbb/irq3 c15 d0 w4 d1 y1 d2 v1 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 46 freescale semiconductor pinout d3 p4 d4 n3 d5 k5 d6 j4 d7 g1 d8 ab1 d9 u4 d10 u2 d11 n6 d12 n1 d13 l1 d14 j5 d15 g3 d16 aa2 d17 w1 d18 t3 d19 t1 d20 m2 d21 k2 d22 j1 d23 g4 d24 u5 d25 t5 d26 p5 d27 p3 d28 m3 d29 k3 d30 h2 d31 g5 d32 aa1 d33 v2 d34 u1 d35 p2 d36 m4 d37 k4 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 47 pinout d38 h3 d39 f2 d40 y2 d41 u3 d42 t2 d43 n2 d44 m5 d45 k1 d46 h4 d47 f1 d48 w2 d49 t4 d50 r3 d51 n4 d52 m1 d53 j2 d54 h5 d55 f3 d56 v3 d57 r5 d58 r2 d59 n5 d60 l2 d61 j3 d62 h1 d63 f4 dp0/rsrv /ext_br2 ab3 irq1 /dp1/ext_bg2 w5 irq2 /dp2/tlbisync /ext_dbg2 ac2 irq3 /dp3/ckstp_out /ext_br3 aa3 irq4 /dp4/core_sreset /ext_bg3 ad1 irq5 /dp5/tben /ext_dbg3 ac1 irq6 /dp6/cse0 ab2 irq7 /dp7/cse1 y3 psdval d15 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 48 freescale semiconductor pinout ta y4 tea d16 gbl/irq1 e15 ci /baddr29/irq2 d14 wt /baddr30/irq3 e14 l2_hit/irq4 a17 cpu_bg /baddr31/irq5 b14 cpu_dbg f13 cpu_br b17 cs0 ac6 cs1 ad6 cs2 ae6 cs3 ab7 cs4 af7 cs5 ac7 cs6 ad7 cs7 af8 cs8 ae8 cs9 ad8 cs10 /bctl1 ac8 cs11 /ap0 ab8 baddr27 c13 baddr28 a12 ale d13 bctl0 af4 pwe0/psddqm0/pbs0 aa5 pwe1/psddqm1/pbs1 ae4 pwe2/psddqm2/pbs2 ad4 pwe3/psddqm3/pbs3 af3 pwe4/psddqm4/pbs4 ab4 pwe5/psddqm5/pbs5 ae3 pwe6/psddqm6/pbs6 af2 pwe7/psddqm7/pbs7 ad3 psda10/pgpl0 ae2 psdwe /pgpl1 ad2 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 49 pinout poe /psdras /pgpl2 ae1 psdcas /pgpl3 ac3 pgta /pupmwait/pgpl4/ppbs w6 psdamux/pgpl5 aa4 lwe0/lsddqm0/lbs0 /pci_cfg0 ac9 lwe1/lsddqm1/lbs1/pci_cfg1 ad9 lwe2/lsddqm2/lbs2/pci_cfg2 ae9 lwe3/lsddqm3/lbs3/pci_cfg3 af9 lsda10/lgpl0/pci_modckh0 ab6 lsdwe /lgpl1/pci_modckh1 af5 loe /lsdras /lgpl2/pci_modckh2 ae5 lsdcas /lgpl3/pci_modckh3 ad5 lgta /lupmwait/lgpl4/lpbs ac5 lgpl5/lsdamux/pci_modck ab5 lwr af6 l_a14/par ae13 l_a15/frame /smi ad15 l_a16/trdy af16 l_a17/irdy /ckstp_out af15 l_a18/stop ae15 l_a19/devsel ae14 l_a20/idsel ac17 l_a21/perr ad14 l_a22/serr af13 l_a23/req0 ae20 l_a24/req1 /hsejsw ac14 l_a25/gnt0 ac19 l_a26/gnt1 /hsled ad13 l_a27/gnt2 /hsenum af21 l_a28/rst /core_sreset af22 l_a29/inta ae21 l_a30/req2 ab14 l_a31/dllout ad20 lcl_d0/ad0 ab9 lcl_d1/ad1 ab10 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 50 freescale semiconductor pinout lcl_d2/ad2 ac10 lcl_d3/ad3 ad10 lcl_d4/ad4 ae10 lcl_d5/ad5 af10 lcl_d6/ad6 af11 lcl_d7/ad7 ab12 lcl_d8/ad8 ab11 lcl_d9/ad9 af12 lcl_d10/ad10 ae11 lcl_d11/ad11 ac13 lcl_d12/ad12 ac12 lcl_d13/ad13 ab13 lcl_d14/ad14 ad12 lcl_d15/ad15 af14 lcl_d16/ad16 af17 lcl_d17/ad17 ae16 lcl_d18/ad18 ad16 lcl_d19/ad19 ac16 lcl_d20/ad20 ab16 lcl_d21/ad21 af18 lcl_d22/ad22 ae17 lcl_d23/ad23 ad17 lcl_d24/ad24 ab17 lcl_d25/ad25 ae18 lcl_d26/ad26 ad18 lcl_d27/ad27 ac18 lcl_d28/ad28 ae19 lcl_d29/ad29 af20 lcl_d30/ad30 ad19 lcl_d31/ad31 ab18 lcl_dp0/c0/be0 ae12 lcl_dp1/c1/be1 aa13 lcl_dp2/c2/be2 ac15 lcl_dp3/c3/be3 af19 irq0/nmi_out a11 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 51 pinout irq7/int_out/ape e5 trst f22 tck a24 tms c24 tdi a25 tdo b24 tris c19 poreset b25 hreset d24 sreset e23 qreq d18 rstconf e24 modck1/ap1/tc0/bnksel0 b16 modck2/ap2/tc1/bnksel1 f16 modck3/ap3/tc2/bnksel2 a15 xfc a18 clkin1 g22 pa0/restart1 /dreq3 ac20 1 pa1/reject1 /done3 ac21 1 pa2/clk20/dack3 af25 1 pa3/clk19/dack4 /l1rxd1a2 ae24 1 pa4/reject2 /done4 aa21 1 pa5/restart2 /dreq4 ad25 1 pa 6 ac24 1 pa7/smsyn2 aa22 1 pa8/smrxd2 aa23 1 pa 9 /s m t x d 2 y26 1 pa10/msnum5 w22 1 pa11/msnum4 w23 1 pa12/msnum3 v26 1 pa13/msnum2 v25 1 pa14/fcc1_rxd3 t22 1 pa15/fcc1_rxd2 t25 1 pa16/fcc1_rxd1 r24 1 pa17/fcc1_rxd0/fcc1_rxd p22 1 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 52 freescale semiconductor pinout pa18/fcc1_txd0/fcc1_txd n26 1 pa19/fcc1_txd1 n23 1 pa20/fcc1_txd2 k26 1 pa21/fcc1_txd3 l23 1 pa 2 2 k23 1 pa 2 3 h26 1 pa24/msnum1 f25 1 pa25/msnum0 d26 1 pa26/fcc1_mii_rx_er d25 1 pa27/fcc1_mii_rx_dv c25 1 pa28/fcc1_mii_tx_en c22 1 pa29/fcc1_mii_tx_er b21 1 pa30/fcc1_mii_crs/fcc1_rts a20 1 pa31/fcc1_mii_col a19 1 pb4/fcc3_txd3/l1rsynca2/ fcc3_rts ad21 1 pb5/fcc3_txd2/l1tsynca2/ l1gnta2 ad22 1 pb6/fcc3_txd1/l1rxda2/l1rxd0a2 ac22 1 pb7/fcc3_txd0/fcc3_txd/ l1txda2/l1txd0a2 ae26 1 pb8/fcc3_rxd0/fcc3_rxd/txd3 ab23 1 pb9/fcc3_rxd1/l1txd2a2 ac26 1 pb10/fcc3_rxd2 ab26 1 pb11/fcc3_rxd3 aa25 1 pb12/fcc3_mii_crs/txd2 w26 1 pb13/fcc3_mii_col/l1txd1a2 w25 1 pb14/fcc3_mii_tx_en/rxd3 v24 1 pb15/fcc3_mii_tx_er/rxd2 u24 1 pb16/fcc3_mii_rx_er/clk18 r22 1 pb17/fcc3_mii_rx_dv/clk17 r23 1 pb18/fcc2_rxd3/l1clkod2/ l1rxd2a2 m23 1 pb19fcc2_rxd2/l1rqd2/l1rxd3a2 l24 1 pb20/fcc2_rxd1/l1rsyncd2/ l1txd1a1 k24 1 pb21/fcc2_rxd0/fcc2_rxd/ l1tsyncd2/l1gntd2 l21 1 pb22/fcc2_txd0/fcc2_txd/ l1rxdd2 p25 1 pb23/fcc2_txd1/l1txdd2 n25 1 pb24/fcc2_txd2/l1rsyncc2 e26 1 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 53 pinout pb25/fcc2_txd3/l1tsyncc2/ l1gntc2 h23 1 pb26/fcc2_mii_crs/l1rxdc2 c26 1 pb27/fcc2_mii_col/l1txdc2 b26 1 pb28/fcc2_mii_rx_er/fcc2_rts / l1tsyncb2/l1gntb2/txd1 a22 1 pb29/l1rsyncb2/ fcc2_mii_tx_en a21 1 pb30/fcc2_mii_rx_dv/l1rxdb2 e20 1 pb31/fcc2_mii_tx_er/l1txdb2 c20 1 pc0/dreq1/brgo7/smsyn2 / l1clkoa2 ae22 1 pc1/dreq2/brgo6/l1rqa2 aa19 1 pc2/fcc3_cd /done2 af24 1 pc3/fcc3_cts /dack2 /cts4 ae25 1 pc4/si2_l1st4/fcc2_cd ab22 1 pc5/si2_l1st3/fcc2_cts ac25 1 pc6/fcc1_cd ab25 1 pc7/fcc1_cts aa24 1 pc8/cd4 /rena4/si2_l1st2/cts3 y24 1 pc9/cts4 /clsn4/si2_l1st1/ l1tsynca2/l1gnta2 u22 1 pc10/cd3 /rena3 v23 1 pc11/cts3 /clsn3/l1txd3a2 u23 1 pc12/cd2 /rena2 t26 1 pc13/cts2 /clsn2 r26 1 pc14/cd1 /rena1 p26 1 pc15/cts1 /clsn1/smtxd2 p24 1 pc16/clk16/tin4 m26 1 pc17/clk15/tin3/brgo8 l26 1 pc18/clk14/tgate2 m24 1 pc19/clk13/brgo7/spiclk l22 1 pc20/clk12/tgate1 k25 1 pc21/clk11/brgo6 j25 1 pc22/clk10/done1 g26 1 pc23/clk9/brgo5/dack1 f26 1 pc24/clk8/tout4 g24 1 pc25/clk7/brgo4 e25 1 pc26/clk6/tout3 /tmclk g23 1 pc27/fcc3_txd/fcc3_txd0/clk5/ brgo3 b23 1 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 54 freescale semiconductor pinout pc28/clk4/tin1/tout2 /cts2 /clsn2 e22 1 pc29/clk3/tin2/brgo2/cts1 /clsn1 e21 1 pc30/clk2/tout1 d21 1 pc31/clk1/brgo1 b20 1 pd4/brgo8/fcc3_rts /smrxd2 af23 1 pd5/done1 ae23 1 pd6/dack1 ab21 1 pd7/smsyn1/fcc1_txclav2 ad23 1 pd8/smrxd1/brgo5 ad26 1 pd9/smtxd1/brgo3 y22 1 pd10/l1clkob2/brgo4 ab24 1 pd11/l1rqb2 y23 1 pd12 aa26 1 pd13 w24 1 pd14/l1clkoc2/i2cscl v22 1 pd15/l1rqc2 /i2csda u26 1 pd16/spimiso t23 1 pd17/brgo2/spimosi r25 1 pd18/spiclk p23 1 pd19/spisel/brgo1 n22 1 pd20/rts4 /tena4/l1rsynca2 m25 1 pd21/txd4/l1rxd0a2/l1rxda2 l25 1 pd22/rxd4l1txd0a2/l1txda2 j26 1 pd23/rts3 /tena3 k22 1 pd24/txd3 g25 1 pd25/rxd3 h24 1 pd26/rts2 /tena2 f24 1 pd27/txd2 h22 1 pd28/rxd2 b22 1 pd29/rts1 /tena1 d22 1 pd30/txd1 c21 1 pd31/rxd1 e19 1 vccsyn d19 vccsyn1 k6 gndsyn b18 table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 freescale semiconductor 55 package description 5 package description the following sections provide the packag e parameters and mechanical dimensions. clkin2 k21 spare4 2 c14 pci_mode 3 ad24 spare6 2 b15 thermal0 4 e17 thermal1 4 c23 i/o power e6, f6, h6, l5, l6, p6, t6, u6, v5, y5, aa6, aa8, aa10, aa11, aa14, aa16, aa17, ab19, ab20, w21, u21, t21, p21, n21, m22, j22, h21, f21, f19, f17, e16, f14, e13, e12, f10, e10, e9 core power l3, v4, w3, ac11, ad11, ab15, u25, t24, j24, h25, f23, b19, d17, c17, d10, c10 ground a2, b1, b2, a5, c5, c18, d4, d6, g2, l4, p1, r1, r4, ac4, ae7, ac23, y25, n24, j23, a23, d23, d20, e18, a13, a16, k10, k11, k12, k13, k14, k15, k16, k17, l10, l11, l12, l13, l14, l15, l16, l17, m10, m11, m12, m13, m14, m15, m16, m17, n10, n11, n12, n13, n14, n15, n16, n17, p10, p11, p12, p13, p14, p15, p16, p17, r10, r11,r12, r13, r14, r15, r16, r17, t10, t11, t12, t13, t14, t15, t16, t17, u10, u11, u12, u13, u14, u15, u16, u17 1 the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 2 must be pulled down or left floating. 3 if pci is not desired, must be pulled up or left floating. 4 for information on how to use this pin, refer to mpc8260 powerquicc ii thermal resistor guide (an2271/d). table 22. mpc8250 pbga package pinout list (continued) pin name ball
mpc8250 hardware specifications, rev. 2 56 freescale semiconductor package description 5.1 package parameters package parameters are provided in table 23 . 5.2 mechanical dimensions this section discusses the tbga and pbga package dimensions. table 23. package parameters package devices outline (mm) type interconnects pitch (mm) nominal unmounted height (mm) zu mpc8250 37.5 37.5 tbga 480 1.27 1.55 vv tbga (pb free) zo 27 27 pbga 516 1 2.25 vr pbga (pb free)
mpc8250 hardware specifications, rev. 2 freescale semiconductor 57 package description 5.2.1 tbga package dimensions figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 tbga package. figure 17. mechanical dimensions and bottom surface nomenclature?480 tbga dim millimeters min max a 1.45 1.65 a1 0.60 0.70 a2 0.85 0.95 a3 0.25 ? b 0.65 0.85 d 37.50 bsc d1 35.56 ref e 1.27 bsc e 37.50 bsc e1 35.56 ref notes: 1. dimensions and tolerancing per asme y14.5m-1994. 2. dimensions in millimeters. 3. dimension b is measured at the
mpc8250 hardware specifications, rev. 2 58 freescale semiconductor package description 5.2.2 pbga package dimensions figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 pbga package. figure 18. mechanical dimensions and bottom surface nomenclature?516 pbga
mpc8250 hardware specifications, rev. 2 freescale semiconductor 59 ordering information 6 ordering information figure 19 provides an example of the freescale part numbering nomenclature for the mpc8250. in addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. for more information, contact your local freescale sales office. figure 19. freescale part number key 7 document revision history table 24 provides a revision history for this template. table 24. document revision history revision date substantive changes 2 7/2009 updated tbga and pbga packaging information. 1 3/2005 document template update 0.9 8/2003 ? ta b l e 2 : modification to supply voltage ranges reflected in notes 2, 3, and 4 ? addition of vccsyn to ?note: core, pll, and i/o supply voltages? following ta b l e 2 ? addition of figure 2 ? addition of note 1 to ta b l e 3 ? ta b l e 4 : changes to ja . addition of jb and jc ? ta b l e 7 , figure 8 : addition of sp42a/sp43a ? figure 3 through figure 8 : addition of notes or modifications ? ta b l e 9 : change to sp10 ? ta b l e 1 4 , ta ble 1 6 , and ta ble 1 8 : removal of pll bypass mode from clock tables ? ta b l e 2 0 and ta b l e 2 2 : addition of note 1 ? addition of spiclk to pc19 in tab le 2 0 and ta b l e 2 2 . it is documented correctly in the mpc8260 powerquicc ii? family reference manual but had previously been omitted from ta b l e 2 0 and ta b l e 2 2 . 0.8 11/2002 ta b l e 2 2 , ?vr pinout?: addition of c18 to the ground (gnd) pin list (page 53) 0.7 10/2002 ta b l e 2 2 , ?vr pinout?: addition of l3 to the core (vddx) pin list (page 53) product code device number process technology package processor frequency die revision level mpc 8250 a c temperature range zu xxx (cpu/cpm/bus) x (a = 0.25 micron) (blank = 0 to 105 c c = ?40 to 105 c) zu = 480 tbga zo = 516 pbga vv = 480 tbga (pb free) vr = 516 pbga (pb free)
mpc8250 hardware specifications, rev. 2 60 freescale semiconductor document revision history 0.6 10/2002 ta b l e 2 2 , ?vr pinout?: corrected ball assignment for the following pins?a12?a17, ta , pd5, pc2. 0.5 9/2002 addition of vr (516 pbga) package information. refer to sections 2.2, 4.2, and 5. 0.4 5/2002 ? ta b l e 2 : notes 2 and 3 ? addition of note on page 8:vddh and vdd tracking ? ta b l e 1 4 : note 3 ? ta b l e 1 6 : note 1 ? ta b l e 1 8 : note 3 0.3 3/2002 ? ta b l e 2 0 : modified note to pin af25. 0.2 3/2202 ? ta b l e 2 0 : modified notes to pins ae11 and af25. ? ta b l e 2 0 : added note to pins aa1 and ag4 (therm0 and therm1). 0.1 2/2002 ? note 2 for table 4 (changes in italics): ?...greater than or equal to 266 mhz, 200 mhz cpm...? ? ta b l e 1 8 : core and bus frequency values for the following ranges of modck_hmodck: 0011_000 to 0011_100 and 1011_000 to 1011_1000 ? ta b l e 2 0 : footnotes added to pins at ae11, af25, u5, and v4. 0 11/2001 initial version table 24. document revision history (continued) revision date substantive changes
mpc8250 hardware specifications, rev. 2 freescale semiconductor 61 document revision history this page intentionally left blank
document number: mpc8250ec rev. 2 07/2009 freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the powerpc name is a trademark of ibm corp. and is used under license. ieee 802.3 and 1149.1 are registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2003, 2005, 2009. information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 2666 8080 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 (800) 441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com

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